Controlled oscillators are used in a variety of integrated circuits. A frequency of an output signal of a controlled oscillator is responsive to a control signal provided to the controlled oscillator. There are various types of controlled oscillators, and one of the most common types is a current controlled oscillator (ICO). A typical ICO is comprised of a controlled current source coupled to a ring of odd number of inverters, an output of an inverter is coupled to an input of a succeeding inverter and an output of the last inverter is coupled to an input of a first inverter. Typical inverters comprise of CMOS transistors, but this is not necessary.
A frequency of an output signal of the ICO is inversely proportional to the delay/switching time of the inverters that form the oscillator. The switching time of an inverter corresponds to a time necessary to charge and discharge an input capacitance of a successive inverter to a level respectively above or below a switching threshold of a successive inverter. The charge and discharge period is determined by the magnitude of current that is used to charge the input capacitance. This current is provided by a controlled current source.
The peak to peak voltage of the output signal (ICOS) of some prior art ICO is relatively low, and there is a need to be amplified. The peak to peak voltage decreases when the frequency of ICOS decreases. Usually, there is a need to amplify ICOS to CMOS compatible levels.
U.S. Pat. No. 5,512,861 of Sharma discloses a buffer stage for use with a current controlled oscillator. This prior art buffer stage, comprising of current controlled buffer (i.e.--A1) 60 followed by a CMOS buffer 45, and a current controlled oscillator (ICO) 30 that is coupled to the buffer stage are schematically described in FIG. 1.
Referring to FIG. 1, ICO 30 comprising adjustable current source (i.e.--S1) 22 and ring oscillator 10. S122 has its high side connected to a positive voltage supply rail VDD supplies, and its low side 5 connected to the high side of a three stage ring oscillator 10. S122 is adjusted by a frequency control signal 8.
Ring oscillator 10 comprises three CMOS inverters 11, 12, 13. At least five inverters within the ring oscillator give a better performance than the use of three inverters. The high side of each inverter is connected to the low side 5 of S122. The low side of each inverter is connected to a negative supply rail VSS. The output of each inverter, starting with the left-most inverter, is connected to the input of the succeeding inverter. The output 25 of the right-most inverter is connected to the input of the left-most inverter.
Inverters 11, 12 and 13 comprising of P-MOS and N-MOS transistors MPB 111, 121, 131 and MNB 112, 122 and 132 respectively. The source terminals of transistors MPB 111, 121 and 131 are connected to low side 5 of S122. The source terminals of transistors MNB 112, 122 and 132 are connected to the negative rail supply VSS. The drain terminals of transistors MPB 111 and MNB 11, MPB 121 and MNB 122, MPB 131 and MNB 132 are connected to form the output terminals of inverters 11, 12 and 13 respectively. The gate terminals of transistor MPB 111, 121, 131 and MNB 112, 122 are connected to from the output terminals of inverters 11, 12 and 13.
S122 and ring oscillator 10 are connected together in such a manner that they form an asymmetrical ICO 30.
The output of ring oscillator 10 is coupled to the input of A160, that is followed by CMOS buffer 45 which is directly supplied by the positive and negative supply rails, VDD and VSS respectively. A160 provides a current controlled buffer output signal (i.e.--A10) 50.
A160 comprises of buffer BA161 comprising of P-MOS and N-MOS transistors TMPB 63 and TMNB 64 and adjustable current source (i.e.--SA1) 61, controlled by control signal 8. The low side of BA161 is connected to the negative supply rail VSS, whilst its high side HA1 is connected to the low side of SA161. The high side of SA161 is connected to the positive supply rail VDD.
The source terminals of transistors MPB 63 and MNB 64 are respectively connected to the positive supply rail VDD and the low side of SA161, and their drain terminals are connected together to form the output terminal of the A160. The gate terminals of transistor TMNB 63 and TMPB 64 are connected to the output of ring oscillator 10.
In order to change the frequency of the signal at the output 55 of CMOS buffer 45, it is necessary to adjust the frequency control signal 8 of S122 and SA161. S122 sources current lb 220 to ring oscillator 10, whilst SA161 sources current Ic 610 to BA161. Adjusting the frequency control signal 8 will cause the magnitudes of both currents Ib 220 and Ic 610 to alter. An increase in the magnitude of current Ib 220 results in an increase in the frequency of the output signal (i.e.--ROS) 25 of ring oscillator 10 and vice-versa.
Simulations and calculations have shown that at low frequencies signal A1050 has an oscillating signal component OSC 501 component and unwanted DC component DCC 502, that causes A1050 to drift. This drift causes buffer 45 to clip and provide output signal 55 that has a much smaller duty cycle than the duty cycle of ROS 25. An example of the measured A1050 and output signal 25 are shown in FIG. 2.
DCC 502 is generated because the amount of current sourced by TMPB 63 is proportional to a logarithm of the voltage at point 5 (i.e.--VP5) 75, while the current sinking capability of TMNB 64 is substantially proportional to (VP5).sup.2. V0575 substantially equals the peak to peak voltage of ROS 25.
Thus, at low frequencies, when VP5 is decreased, TMNB 63 starts to source more current than TMPB 64 can sink. TMPB64 is forced to decrease the voltage potential between its source and drain while TMNB 63 is forced to increase the voltage potential between its source and drain, DCC 502 reflects that increment.
There is a need to provide an output buffer stage for a current controlled oscillator that provides a buffered signal having a duty cycle that is substantially equal to the duty cycle of the output signal of the ICO over a large range of frequencies.
There is a need to provide an output buffer stage for a current controlled oscillator that provides a buffered signal having a duty cycle that is substantially equal to the duty cycle of the input signal.